A Case for Leveraging 802.11p for Direct Phone-to-Phone Communications

WiFi cannot effectively handle the demands of device-to-device communication between phones, due to insufficient range and poor reliability. We make the case for using IEEE 802.11p DSRC instead, which has been adopted for vehicle-to-vehicle communications, providing lower latency and longer range. We demonstrate a prototype motivated by a novel fabrication process that deposits both III-V and CMOS devices on the same die. In our system prototype, the designed RF front-end is interfaced with a baseband processor on an FPGA, connected to Android phones. It consumes 0.02uJ/bit across 100m assuming free space. Application-level power control dramatically reduces power consumption by 47-56%.Singapore-MIT Alliance for Research and TechnologyAmerican Society for Engineering Education. National Defense Science and Engineering Graduate Fellowshi

Novel techniques for fully-intergrated RF CMOS phase-locked loop frequency synthesizer

In this thesis, the design of a fully integrated RF CMOS phase-locked loop is explored. The goal of this research is to provide solutions for the problems associated with the VCO and the frequency divider in the RF CMOS phase-locked loop.Doctor of Philosophy (EEE

An in-phase-coupled class-C quadrature VCO with tunable phase error

This letter presents the design and analysis of a novel in-phase-coupled (IPC) Class-C Quadrature Voltage-Controlled Oscillator (QVCO) with tunable phase error. The IPC QVCO employs a novel coupling structure that generates in-phase coupling signal while consuming negligible power itself. IPC scheme enables the QVCO to achieve better phase noise and phase error compared to that of the conventional QVCO. The phase error of the proposed IPC QVCO is also tunable. The proposed IPC QVCO is fabricated using 0.18 μm CMOS technology and the measured output frequency range is from 2.5 to 2.97 GHz. At 2.623 GHz, with 3.6 mW power consumption, the phase noise at 1 MHz offset achieves -126.8 dBc/Hz while the phase error before phase error tuning is 0.5 °. The measured phase error tuning range is ±17°.Accepted versio

A 40 GHz CMOS PLL with -75-dBc reference spur and 121.9-fs rms jitter featuring a quadrature sampling phase-frequency detector

The high phase noise (PN) of CMOS millimeter-wave oscillators has encouraged the adoption of wide loop bandwidth for an integer-N phase-locked loop (PLL). This article proposes a quadrature sampling phase-frequency detector (QS-PFD) to disengage the tradeoff between spur rejection and loop bandwidth. With the introduction of an auxiliary path for phase detection, the spur generated by the main path is canceled without incurring extra power or degrading the loop stability. The high gain of the QS-PFD attenuates its jitter contribution to the loop. The QS-PFD enables fast frequency detection and lock detection. Implemented in 40-nm CMOS technology, the proposed PLL shows a -75-dBc reference spur, -101.5-dBc/Hz PN at a 1-MHz offset, and a minimum integrated jitter of 121.9 fs $_{{rms}}$ (10 kHz-100 MHz) at 38.2 GHz with a division ratio of 128. The lock detection time is at the microsecond level. The proposed PLL consumes 23.6 mW from a 1.1-V power supply, leading to a figure of merit (FoM) of -245 dB.Ministry of Education (MOE)Submitted/Accepted versionThis work was supported by the Singapore Ministry of Education Academic Research Fund Tier 2 under Grant MOE2019-T2-1-114

A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector

This letter introduces a novel phase detector (PD) for suppressing the reference spur in a 40 GHz integer-N phaselocked loop (PLL). Coined as a spur-compensation phase detector (SCPD), the proposed SCPD duplicates itself to an auxiliary path for an edge-combined phase alignment, such that the spurs generated by the two paths mutually compensate for each other, achieving a net effect of spur canceling. Implemented in a 40-nm CMOS technology, the proposed PLL shows less than −71.4-dBc reference spur, −98- and −117-dBc/Hz phase noise at 1- and 10-MHz offset, respectively, and a minimum rms jitter of 114 fs (10 k–100 MHz). It consumes 23.4-mW power from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB.Ministry of Education (MOE)Submitted/Accepted versionThis work was supported by the Singapore Ministry of Education Academic Research Fund Tier 2 under Grant MOE2019-T2-1-114

A 6bit 1.2GS/s symmetric successive approximation energy-efficient time-to-digital converter in 40nm CMOS

This work presents a 6bit 1.2GS/s symmetric successive approximation (SSA) energy-efficient time-to-digital converter (TDC). The delay offset of the successive approximation (SA) TDC has been alleviated by employing the balanced architecture and optimizing the phase detector (PD). Size-optimized inverter chain is deployed as the delay unit with good linearity to increase the conversion rate and reduce the power consumption. In addition, dynamic logic is implemented to further improve the speed and energy efficiency. As a proof-of-concept design, the TDC is verified by post-layout simulation (Transient noise + Monte Carlo (MC)) in 40nm low power CMOS technology, achieving 0.98LSB /1.03LSB worst case differential nonlinearity (DNL)/integral nonlinearity (INL) and 0.014pJ/conversion-step figure-of-merit (FOM). The simulated single-shot precision (SSP) of the proposed TDC is 0.71 LSB.Ministry of Education (MOE)Accepted versionThis work was supported by the Singapore Ministry of Education Academic Research Fund Tier 2 (MOE2019-T2- 1-114)

A crosstalk-immune sub-THz All-surface-wave I/O transceiver in 65-nm CMOS

A surface-wave I/O transceiver is proposed and validated at 140 GHz in 65 nm CMOS. By generating, modulating and propagating surface plasmonic signal, the all-surface-wave I/O is prototyped with crosstalk-immune owning to the sub-wavelength localization of electromagnetic wave at the metal/dielectric interface. A four-way surface-wave signal source is power-combined via coupled oscillator network. A surface-wave modulator is realized by stacking two split-ring-resonator (SRR) unit-cells with opposite placement. It is further integrated into the all-surface-wave I/O with a surface-wave transmission line and matching converter. Measured results show that the proposed dual-channel I/O delivers a localized 140 GHz surface-wave signal, demonstrating crosstalk-immune on-chip transmission by supporting 13.5 Gb/s data-rate communication with 2.6 PJ/bit Power efficiency and a bit-error rate less than 10^(-12).MOE (Min. of Education, S’pore)Accepted versio

Cell-based variable-gain amplifiers with accurate dB-linear characteristic in 0.18 µm CMOS technology

A simple and robust “cell-based” method is presented for the design of variable-gain amplifiers (VGAs). The proposed unit cell utilizes a unique gain compensation method and achieves accurate dB-linear characteristic across a wide tuning range with low power consumption and wide bandwidth. Several such highly dB-linear unit cells can be cascaded to provide the required gain range for a VGA. To prove the concept, single-cell, 5-cell, 10-cell and 15-cell reconfigurable VGAs were fabricated in a standard 0.18 μm CMOS technology. The measurement results show that the 10-cell VGA achieves a gain range of 38.6 dB with less than 0.19 dB gain error. The 15-cell VGA can either be used as reconfigurable VGA for analog control voltage or tunable PGA for digital control stream, with the flexibility of scaling gain range, gain error/step and power consumption. For the VGA at highest gain setting, it consumes 1.12 mW and achieves a gain range of 56 dB, gain error less than 0.3 dB.Accepted versio

A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS

Low-power and low-jitter equalization techniques become increasingly crucial for the wire-line receivers operating at data rates more than tens of gigabits per second. This brief reports an inductorless and power-efficient 32-Gb/s hybrid analog equalizer. The hybrid analog equalizer utilizes a triple-gate control to achieve equalization over a range of channel loss resulting in an inductorless and area-efficient design. The triple-gate controls entail that a low-frequency equalization is achieved in addition to the intermediate and high-frequency equalization, at minimum area overhead. The prototype is realized in a 65-nm CMOS, occupying a compact active area of 0.013 mm2. The maximum equalization achieved is 21 dB at Nyquist with a measured peak-to-peak data jitter of 5.25 ps (0.17 unit interval) at 32 Gb/s for a 231 - 1 pseudorandom bit sequence signal. The measurement shows a vertical eye-opening recovery rate of up to 61% at 32 Gb/s, for a channel loss of 21 dB. The prototype exhibits a competitive power efficiency of 0.53 mW/Gb/s under a supply voltage of 1.2 V.MOE (Min. of Education, S’pore

A 20.2–57.1 GHz Inductor-less Divide-by-4 Divider Chain

In this paper, a 20.2 GHz to 57.1 GHz inductor-less divide-by-4 divider chain based on STMicroelectronics 65nm CMOS technology is presented. As the frequency increasing to millimeter-wave (mm-wave), the divider design becomes more and more challenging, especially in terms of locking range and power consumption. We proposed a divide-by-2 current mode logic (CML) divider with dynamic loads and merged clock switches, followed by a divide-by-2 injection-locked frequency divider (ILFD) with multi-phase input, to obtain compact area and wide locking range with low power consumption. The measurement results show that the locking range of the divider chain is from 20.2 GHz to 57.1 GHz, or 95% without tuning, with 2dBm input power. The measured power consumption is about 11.5mW at 1.2V supply. Since no inductor is used in our dividers, the area of core circuit is only 30μm by 50 μm